Ternary ROM

Interactive model-to-GDS flow for mask-locked ternary inference chips

What is a Ternary ROM?

Ternary ROM encodes neural network weights into mask-programmed silicon. Instead of fetching weights from SRAM, weights are burned permanently into ROM cells—one cell per weight.

Each weight is quantized to ternary: {−1, 0, +1} (2 bits per weight = 8× memory reduction). Three cell types handle all weights:

  • ROM_PLUS: Drives bitline to VDD when selected (weight = +1)
  • ROM_MINUS: Drives bitline to GND when selected (weight = −1)
  • ROM_ZERO: Empty space—no transistors, zero leakage (weight = 0)

Why ternary ROM? No multipliers needed (just add/subtract/skip). No weight fetches from SRAM. ~60% of weights are zero → zero static power for those cells.

Ternary Weight → Cell Row Weight +1 −1 0 ROM Cell PLUS MINUS ZERO Bitline → VDD → GND → Z Each weight → one cell instance Multiple cells per bitline accumulate (OR tree)
Property Ternary ROM Conventional (SRAM + FP16)
Weight storage Mask-programmed ROM SRAM
Bits per weight 2 16
Memory reduction 8× 1× (baseline)
Multiply operation Eliminated (add/sub/skip) Required
Gate count (MAC) 103 360
Energy per op 22 pJ 194 pJ
Weight update New mask ($200K) Rewrite SRAM (free)
Idle leakage Zero for ~60% of cells (weight=0) Full SRAM leakage

The Three Cells: Truth Table & Symbols

ROM_PLUS

Function: Drives BL to VDD (weight = +1)

Transistors: 2 (PMOS pull-up)

Leakage: ~2.37 pA (28nm)

Truth Table

WL BL
0 Z (undriven)
1 VDD ✓
ROM_PLUS Symbol VDD PMOS WL BL →

Verilog

module ROM_PLUS_X1 (WL, BL);
  input WL;
  output BL;

  assign BL = WL ? 1'b1 : 1'bz;
endmodule

BL = Z

ROM_MINUS

Function: Drives BL to GND (weight = −1)

Transistors: 2 (NMOS pull-down)

Leakage: ~2.37 pA (28nm)

Truth Table

WL BL
0 Z (undriven)
1 GND ✓
ROM_MINUS Symbol NMOS WL BL GND →

Verilog

module ROM_MINUS_X1 (WL, BL);
  input WL;
  output BL;

  assign BL = WL ? 1'b0 : 1'bz;
endmodule

BL = Z

ROM_ZERO

Function: No cell (weight = 0)

Transistors: 0 ✓

Leakage: 0 pA ✓

This is the magic: 45–60% of weights are zero, eliminating leakage by design.

Truth Table

WL BL
0 Z (undriven)
1 Z (undriven) ✓
ROM_ZERO Symbol Empty Space (No transistors)

Behavior

// No cell instantiated.
// Wire contribution: none.
// Bitline remains undriven
// when this weight is selected.

BL = Z (always)

Cell Library Explorer

Select a process to explore its cell variants (drive strength, Vt flavor, leakage, delay).

Cells: —
Voltage: —
Category: —
Total Leakage (all types): —
Cell Name Type Vt Drive W × H (µm) Area (µm²) Transistors Leakage (pA) Delay (ns)
Select a process to view cells.

Leakage Comparison (pA)

Verilog Browser

Live-parsed module listings from cells.v for sky130 and generic_28nm.

Loading modules…

Physical Layout Viewer

Interactive footprint visualization parsed from LEF. Shows pin locations and cell dimensions.

WL (Metal1)
BL (Metal2)

Example: 8×8 Ternary MAC (TinyTapeout)

A real 8×8 multiply-accumulate unit with ternary weights. These weights are literally wired to ROM cells.

Weight Map (8×8)


          

        


        

          
Summary

          

        

      


      

        
Netlist Browser (ternary_mac.v)

        

          
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Flow: Model → Tape-Out

      
The complete path from trained model to silicon.


      
        
        
        Trained
        Model
        (PyTorch)

        
        
        weights

        
        
        Ternarize
        BitNet b1.58
        {−1,0,+1}

        
        

        
        
        Netlist
        Gen
        ROM cells

        
        

        
        
        OpenROAD
        P&R + GDS

        
        

        
        
        Tape-Out
        GDS
        → Silicon

        
        Input: weights.npz
        Cosine sim > 0.95
        Structural Verilog
        Place, route, verify
        $200K–2M cost

        
        Parallel: Sensitivity Analysis
        → Identifies layers needing INT8 SRAM (mixed precision)